I have to connect 3 DSP's with Virtex-6, data flash and boot flash all in a single local bus. My question is whether I have different control signals from each DSP to the FPGA or a single connection?
Please let me know on whether the FPGA, data flash and boot flash need to be shared among all the DSPs or not. In case you want them to use as shared resources then you need to short all the control signals of DSP and connect it to FPGA and other devices.
Yes, the boot flash, data flash, FPGA ( Virtex-5) and the 3 DSP's are all sharing the same bus. If the control signals also have to be shorted, that means, is the RD signal(as example) of all the 3 DSPS connected to one single IO of the FPGA? So the processors in the same bus are differentiated by ID0-2.
And another question I wanted to ask(regarding a different project) was about the link ports, Im only using link port 0 connected with the FPGA. So can I leave the other 3 link ports completely unconnected? What should I do with the CLKIN pins and the CMP0 and BMP0 pins?? I read the reference schematic and found a few of the DATA pins connected to 2.5V. Why is that important?
Can anyone reply to this question please? Its really important and urgent!
Your understanding is correct about the FPGA interface. Regarding the link port, the unused link port input pins should be connected to VDDIO/VSS. These pins should not be left floating. Please refer the pin function description on the datasheet for more details. You may use the application note on the below link for system design guidelines:
I had one more question about the same project. We have connected a 16-bit SRAM with the DSP. How do we connect the address lines for the SRAM. Its a 1Mx16 device with A0 to A19 address lines. I have right now connected A0 of SRAM to A0 of DSP and so on. Can you confirm this is correct.
Application notes EE-210 and EE-201 available at the link attached should answer all your questions in regards to the SDRAM interface for your system and selected memory configuration.
I think that your connection is correct. You need to configure the SYSCON register MEMWIDTH bits to 32-bit for this case. The processor may access the memory as 32-bit one only.
Thank you for your help. SRAM is working fine. My external bus is working at 120MHz clock and I have a SRAM, Flash and FRAM on the same bus. Flash that I have used has an access time of 95ns. The syscon register allows a wait cycle of max 3 which doesnt serve my purpose for accessing the flash. So how is it possible to run the flash at lower clock speeds? The external wait signal ACK is not mapped with the ReadyBusy pin of the flash. Can you help me out with this?
If the flash is connected to the BMS pin as well then you can access the flash with more wait states. You can configure the DPx register Device type bits to use Boot EPROM. This will use the BMS pin for accessing the flash.
I have one boot flash and one data flash in the same bus. Boot flash is connected with BMS pin. The Data flash has its chip select connected with MS1 pin of DSP. Any other option of reducing the speed?
For the flash which is connected to MS1 you need to use the external ACK pin only to increase the wait states. I am not sure on whether the ACK pin is connected to the memory in your interface.
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