Reading post TDD Mode Switching Time , my understanding is that standard TDD mode with dual synth has the fastest switching time among standard TDD modes. How is this compared to TDD mode using fast lock profiles? Using dual synth can eliminate PLL Lock time and VCO calibration time, this won't hurt performance right?
In UG570 page 7, it's mentioned that "Others are dependent on the carrier frequency, temperature, or other parameters and need to run initially and when certain events occur (such as changing the carrier frequency more than 100 MHz)."
Does this mean that if the frequency hops within 100MHz band, I don't need to enable the VCO calibration? If not, what is the max frequency separation between hopped frequencies to avoid VCO calibration? Thanks.