I am trying to get the SPI working in slave mode, but am stuck.
The SPI is not responging at all! No output, not status bit change.
Table 8. SPI Slave Mode Timing (PHASE Mode = 0) of the ADuC datasheet says
"SCLOCK low pulse width has to be (SPIDIV + 1) × tHCLK"
Should the SPIDIV register be set to match the SPI Clock frequency of the master?
CSB is grounded. Is this wrong?
In SPICON what does bit 9 'Slave Select Input Enable' be set to.
The docoment says "Set by user in master mode to enable the output. Cleared by user to disable master output." but setting it either way dose'nt help.
Thanks in advance,