Hi, I am trying to figure out BF60x's ACM performance, can ACM generate low jitter clock to drive 5 MSPS SAR dual channel ADC?, how good is it? thanks!
In BF60x, the ACM clock is calculated as ACLK = SCLK1 / (CKDIV + 1) allowing odd dividers as well, thereby increasing the ACM clock granularity.
Hi, I wanted to know 60x ACM capability to drive ADC sampling clock, it's supposed to able to drive ADC as it's name suggest but in the manual I couldn't find any jitter parameters which is critical for ADC uses, it could be unfair to assume that it has large jitter just as other clock sources.
I believe it has good enough jitter to drive 12~14bit SAR ADC as it uses SPORT and not slower serial buses, together with max system clock of 60x, it's is the upper limit of data transfer from ADC to 60x, so I assume the ACM has good enough clock to drive such application before ADC SNR degrades too much at max conversion rates. SAR ADC the upper conversion rates are around 3~5 Msps, or 60x ACM are designed for Ksps applications?
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