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Configuring AD9528 device tree VCXO on AD9371 Eval Board

Question asked by ssloboda on Nov 29, 2016
Latest reply on Dec 1, 2016 by ssloboda

Hi,

 

I've been trying to get the AD9371 kernel driver to work properly with a 125MHz VCXO on the eval board rather than the stock 122.88MHz crystal. I cannot use the 122.88MHz crystal because I need to use a 10MHz external reference clock. I generated a profile (attached) using the AD9371 filter wizard and have been trying to modify the device tree to use the values from the profile. I've also been referencing AD9371 Evaluation Board VCXO selectionAD9371 Device Driver Customization [Analog Devices Wiki], and AD9528 Low Jitter Clock Generator Linux Driver [Analog Devices Wiki] when trying to set the device tree values. My current device tree source file is also attached. Currently I am running into the following error which leads me to believe that there is something wrong with my AD9528 configuration:

 

kern :info : ad9371 spi32766.1: ad9371_probe : enter
kern :info : ad9371 spi32766.1: ad9371_probe : of_clk_get_by_name() deferred
kern :info : iio iio:device2: ad9528 setup
kern :info : mmcblk0: mmc0:aaaa SL08G 7.40 GiB
kern :info : mmcblk0: p1 p2 p3
kern :warn : ad9528: probe of spi32766.0 failed with error -110
kern :info : NET: Registered protocol family 17
kern :notice: Registering SWP/SWPB emulation handler
kern :info : axi-hdmi 70e00000.axi_hdmi: No connectors reported connected with modes
kern :info : [drm] Cannot find any crtc or sizes - going 1024x768
kern :info : Console: switching to colour frame buffer device 128x48
kern :info : axi-hdmi 70e00000.axi_hdmi: fb0: frame buffer device
kern :info : [drm] Initialized axi_hdmi_drm 1.0.0 20120930 on minor 0
kern :info : ad9371 spi32766.1: ad9371_probe : enter
kern :info : ad9371 spi32766.1: ad9371_probe : of_clk_get_by_name() deferred
kern :err : of_clk_src_onecell_get: invalid clock index 1
kern :err : ERROR: could not get clock /fpga-axi@0/axi-jesd-gt-rx-tx@44a60000/link@0:conv(0)
kern :info : asoc-simple-card fpga-axi@0:adv7511_hdmi_snd: adv7511 <-> 75c00000.axi-spdif-tx mapping ok
kern :info : ad9371 spi32766.1: ad9371_probe : enter
kern :info : ad9371 spi32766.1: ad9371_probe : of_clk_get_by_name() deferred
kern :err : of_clk_src_onecell_get: invalid clock index 1
kern :err : ERROR: could not get clock /fpga-axi@0/axi-jesd-gt-rx-tx@44a60000/link@0:conv(0)
kern :info : input: gpio_keys as /devices/soc0/gpio_keys/input/input0
kern :info : ad9371 spi32766.1: ad9371_probe : enter
kern :info : ad9371 spi32766.1: ad9371_probe : of_clk_get_by_name() deferred
kern :info : rtc-pcf8563 5-0051: setting system clock to 2016-11-29 11:05:56 UTC (1480417556)
kern :err : of_clk_src_onecell_get: invalid clock index 1
kern :err : ERROR: could not get clock /fpga-axi@0/axi-jesd-gt-rx-tx@44a60000/link@0:conv(0)

 

 

I am attempting to use 125MHz VCXO and 125MHz DEV_CLK. According to the VCXO selection guide, the values I'm using (M1 = 3, N2 = 30, R1 = 3, chDIV = 10) should allow that. Also, the values that I'm using for PLL1's dividers (R = 10, feedback-div = 125) should allow PLL1 to lock to the 10MHz ref clock. Could someone please help me understand how to correctly configure the device tree for the AD9528 and/or AD9371 in my use case with 125MHz VCXO?

 

 

Here are the device tree attributes I've modified/added so far:

 

ad9528-1@0 {

adi,vcxo-freq = <0x7735940>;

adi,refa-r-div = <0xa>;
adi,pll1-feedback-div = <0x7d>;

 

adi,pll2--vco-diff-m1 = <0x3>;
adi,pll2-n2-div = <0x1e>;
adi,pll2-r1-div = <0x3>;

 

channel@13 {

/* DEV_CLK */
adi,channel-divider = <0xa>;

};

};

 

ad9371-phy@1 {

adi,clocks-device-clock_khz=<125000>;
adi,clocks-clk-pll-vco-freq_khz=<10000000>;
adi,clocks-clk-pll-vco-div=<2>;
adi,clocks-clk-pll-hs-div=<4>;

 

adi,rx-profile-adc-div=<1>;
adi,rx-profile-rx-fir-decimation=<2>;
adi,rx-profile-rx-dec5-decimation=<5>;
adi,rx-profile-en-high-rej-dec5=<1>;
adi,rx-profile-rhb1-decimation=<1>;
adi,rx-profile-iq-rate_khz = <125000>;
adi,rx-profile-rf-bandwidth_hz=<100000000>;
adi,rx-profile-rx-bbf-3db-corner_khz=<100000>;


adi,obs-profile-adc-div=<1>;
adi,obs-profile-rx-fir-decimation=<2>;
adi,obs-profile-rx-dec5-decimation=<5>;
adi,obs-profile-en-high-rej-dec5=<1>;
adi,obs-profile-rhb1-decimation=<1>;
adi,obs-profile-iq-rate_khz = <125000>;
adi,obs-profile-rf-bandwidth_hz=<100000000>;
adi,obs-profile-rx-bbf-3db-corner_khz=<50000>;


adi,sniffer-profile-iq-rate_khz = <125000>;


adi,tx-profile-dac-div=<1>; /* enum value 1 --> 2.5 */
adi,tx-profile-tx-fir-interpolation=<1>;
adi,tx-profile-thb1-interpolation=<2>;
adi,tx-profile-thb2-interpolation=<2>;
adi,tx-profile-tx-input-hb-interpolation=<1>;
adi,tx-profile-iq-rate_khz = <125000>;
adi,tx-profile-primary-sig-bandwidth_hz=<40000000>;
adi,tx-profile-rf-bandwidth_hz=<100000000>;
adi,tx-profile-tx-dac-3db-corner_khz=<100000>;
adi,tx-profile-tx-bbf-3db-corner_khz=<50000>;

};

 

clocks {

clock@0 {

clock-frequency = <0x989680>;

};

};

 

 

Thanks,
Steven

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