Hi there，may I ask a question about adar7251's pllfilt ? I forgot to design the pll loop filter between pllfilt pin and pllgnd pin , and only tied pllfilt pin and pllvdd to high(3.3v), and pllgnd to agnd. Now when I am testing my board, the adc has no output, and fault pin keeping low (the fault pin has pull up to 3.3v via a 10k resistor . Now I want to know could my board work well in this case by some kinds of spi config? What about bypass pll? If bypass pll could work, should the input freq of mclkin pin be 115.2mhz?(I did not use the external crystal, the clock is provided by a FPGA output , so the freq is programable) I just tried this mode and it did not work, so I also confused whether I config a correct spi sequence or not. Could anyone suggest a simple spi sequence to check?
Could you help me with my questions above? I would be appreciated for your attention. Thank you.