ADV7343 is used with 27MHz pixel clock and 13,5MHz pIxellane Clock and working fine.
can the ADV7343 be used in PAS SD timings others like with 1728x625,e.g. 1024 and how to?
Best regards, Bernd
I don’t understand the requirement clearly. Could you please elaborate?
Are you referring the ADV7343 CVBS output configurations?
he is asking for me, so i can specify more i hope:
yes, it is:
-CVBS output configuration
in PAL you have 64mys for one line. We found by try and error, even if specs for SD pal are ~720-866pixels you need the FULL 1728pixels (referres to 27MHZ clocking for 64mys) to display the image.
The image is downsized as result.
So the question is (as our driver can only output 1024 pixels) if there is a workaround to use the ADV7343 in another mode so it does not need the full 1728pixels per line input...
Are you trying to go with an 8 or 16 bit bus?
If your driver can only output 1024 pixel per line then the best it will be able to do is the 864 pixels needed for PAL. The formats are limited to what is shown in the data sheets.
we want the 24bit RGB with HW synchronisation,
but i also tried 8bit embedded, of course there you run faster in the limit of the 1024 pixels..
but when you mention the pixel formats modes in the datasheet:
To me it appears that this are Output formats rather input, how whould i configure the PAL SD INPUT format?
I cannot find something in the manual that changes the behaviour of the device to differ from the desribed above
(downsampling from always the biggest resolution)
Table 82 shows how to set up for RGB in, CVBS out. You cannot change the resolution. The input timing will be the output timing.
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