I currently have two designs that implement the JESD204B protocol. One is using the ADI FMCADC2 reference design (JESD is implemented in three separate blocks) and the other is using the JESD cores that come with Vivado (2 blocks).
Unfortunately, both designs are on different hardware, so that is definitely a variable.
When running on the Xilinx cores we get the following error:
cf_axi_jesd204b_gt 43c00000.system_axi_ad9625_jesd_0_support: Failed get EYESCAN_RATE/RXOUT_DIV
cf_axi_jesd204b_gt: probe of 43c00000.system_axi_ad9625_jesd_0_support failed with error -22
Does this point to a SW/core problem or is this a PCB level issue?
At a high level, how are the ADI vs. Xilinx implementations different? Is there a way to configure both the same way?