figure 47 in page 30 of HMC832 datasheet shows the the SEN line is low at the falling edge number 23 of SCK line. shouldn't it be pulled low at the beginning of data transition ?
i attached an image of the figure.
There is no timing requirement to set SEN low before asserting SCK clocks. On every rising SCK edge the HMC832 will clock in SDI data but it is the rising SEN edge that latches the previous 32 bits. You can clock in any number of bits but it is only the last 32, as defined by the rising SEN edge that matter. If the last three bits A2:A0 are zero the HMC832 is enabled and will write D23:D0 to the register defined by R4:R0. There is a minimum SEN low and high time of 10ns (t3 and t4).
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