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ADAS3022 FGPA code question

Question asked by AdrianC Employee on Nov 25, 2016
Latest reply on Nov 25, 2016 by AdrianC

Received over e-mail:

I want to ask about your ADAS3022 FPGA implementation. I'm using ADAS3022 with Xilinx Spartan 3a FPGA and as a base I use your verilog code. I want to ask how you implemented SPI interface for ADAS3022. I try to analize SPI rx/tx code: 

 

always @(negedge adc_clk_i)                                 // Process for receiving data from ADAS3022

begin

    if (reset_i == 1'b1)

    begin

        rx_reg      <= 16'h0;

    end

    else if(SCLK_en == 1'b1)

    begin

        rx_reg      <= { rx_reg[14:0], MISO_i };

    end

end

 

always @(negedge adc_clk_i)                                 // Process for transmitting data to ADAS3022

begin

    if (reset_i == 1'b1)

    begin

        tx_reg_d    <= 16'h0;

    end

    else if(SCLK_en == 1'b1)

    begin

        tx_reg_d    <= { tx_reg_d[15:0], 1'b0 };

    end

    else

    begin

        tx_reg_d    <= tx_reg;

        tx_reg_d[16]<= tx_reg[15];

    end

end

 In my environment adc_clk_i is 10Mhz and it seems that this code doesn't work for me. After debugging with logic analizer it seems that there is shift between  ADC DIN and CLK. The falling edge of CLK occures on DIN falling edge.

 

Is this code is designed only for 50Mhz clock ? Can you help me with getting correct SPI waveform where CLK falling edge occures on middle of DIN data bit. 

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