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AD2S1210 Parallel Port / Clear Fault Register timing

Question asked by sss on Nov 21, 2016
Latest reply on Nov 30, 2016 by jcolao

Hi all,

 

In the datasheet @ AD2S1210, Figure 31. Parallel Port—Clear Fault Register.

"t2" , "t9" are correct ?
We are confused.

 

TIMING SPECIFICATIONS @ Table 2, following is description.
t2 : Delay CS falling edge to WR/FSYNC rising edge
t9 : Delay between successive write cycles

 

Best regards,
sss

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