AnsweredAssumed Answered

AD9670 Multiple chips synchronization

Question asked by tnatf on Nov 21, 2016
Latest reply on Nov 24, 2016 by tnatf


I experienced some difficulties to synchronize multiple AD9670 chips which are fed by the same copy of sampling clock and trigger signal (delays between copies are < 1 ns)

For example, the ADCs configuration set to :

- RF decimation decimate by 2,

- output set to a decimation rate of 4,

- demodulator off,

- 16 bit word, 1 ch/lane

-  a sampling frequency of 25 MHz (40 ns period),

- the trigger signal is one sampling clock period centered on failling edge of the sampling clock (the setup and hold timings are so respected)


In this case, the DCO has the same frequency as the sampling frequency.

We can observe the phase of the DCO of two different chips with 20 ns delay.


Considering the case above, are  DCO and FCO Propagation Delay respecting

(tCPD) =tFCO+ (tSAMPLE/28) and tFCO = 10.8 +/- 1.5 tDCO as shown in datatsheet Figure 2?


What is the ADC_TRIG generation rule to keep a FCO signal without phase shift ? (if there is a phase shift, the SERDES mecanism have to resynchronize...) ?


What are the good pratices to synchronize multiples chip of AD9670 and be able to date samples ?