AnsweredAssumed Answered

AD9361 DATA_CLK and RX_FRAME duty cycle

Question asked by Usher on Nov 18, 2016
Latest reply on Nov 23, 2016 by Vinod

Hello ADI people,


In UG-570, there has a clear description says that RX_FRAME should be 50% duty cycle. However, what I observed via LA is not meet the description. Please refer to below questions I have and thanks for your supporting in advance.


1) Below image shows DATA_CLK duty cycle from LA, UG-570 doesn't mention duty cycle information for it. But I assume it should be 50%. Any possible reasons to make it wrong if my assumption is correct?



2) Below one is for RX_FRAME. As you can see, the duty cycle is also not 50%. Both RX_FRAME and DATA_CLK from AD9361 directly so I am not sure what causes it.



3) Final, below screen capture is from UG-570. In 2R2T, dual port and FDD mode BBP should receives DATA_CLK, RX_FRAME and RX_IQ just like below pattern from AD9361, am I right? If I am correct, why I get the pattern just like previous two questions instead of below picture? Following question is that should I adjust register 0x006 to create right pattern for BBP?