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Multiply input SPDIF clock: looking for advice

Question asked by awdee0 on Nov 18, 2016
Latest reply on Dec 7, 2016 by Jithul_Janardhanan

I'm working with an ADSP-21489 EZ Board. I've successfully ported the old "SPDIFToAnalogTalkthruwithSRC" example over to CCES from VDSP.

 

I would like to upsample the output 4X relative to the SPDIF input. I have already written/tested interpolating routines on other platforms that I'm porting over for use on this project, so I just need to figure out how to get the hardware clocks/interrupts to work the way I need them to.

 

In theory, I would grab the clock signal from the SPDIF input, generate a new timer signal that's a 4X multiple of the SPDIF input clock, and set up my interrupts so that the output frames are sent to the 1939 DAC with the new timer (at the 4x rate). Trouble is, I'm new to the ADSP-21489 (and the EZ-board/1939), so I'm not sure what the best path would be for this particular platform.

 

I'm not looking for working code (although that would be cool), just the right "sequence of mechanisms" (and processor-specific features/terminology) that would make this work. Any suggestions would be appreciated.

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