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FMCDAQ2 in ZC706 error in building HDL reference design

Question asked by nousername on Nov 18, 2016
Latest reply on Nov 21, 2016 by nousername

Hi,I have been struggling to build the reference HDL design for FMCDAQ2-EBZ with ZC706. I am using VIvado 2016.2 and when i try to build my libraries first and then my project I face the following error. Btw i have been using the latest ref design "hdl_2016_r1".

 

ERROR: [BD 5-216] VLNV <xilinx.com:ip:clk_wiz:5.2> is not supported for the current part. The latest supported version for this part is:5.3
ERROR: [Common 17-39] 'create_bd_cell' failed due to earlier errors.

while executing
"create_bd_cell -type ip -vlnv xilinx.com:ip:clk_wiz:5.2 sys_audio_clkgen"
invoked from within
"set sys_audio_clkgen [create_bd_cell -type ip -vlnv xilinx.com:ip:clk_wiz:5.2 sys_audio_clkgen]"
(file "../../../projects/common/zc706/zc706_system_bd.tcl" line 106)

while executing
"source $ad_hdl_dir/projects/common/zc706/zc706_system_bd.tcl"
(file "system_bd.tcl" line 2)

while executing
"source system_bd.tcl"
(procedure "adi_project_create" line 97)
invoked from within
"adi_project_create daq2_zc706"
(file "system_project.tcl" line 8)

 

Thanks.!

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