Hello ADI folks,
The parallel port of AD9361 is configured as below for 2R2T, DDR, FDD, dual port mode on my project.
0x010 = 0xCC
0x011 = 0x00
0x012 = 0x02
However, I am not sure how to allocate IQ for both TX1/TX2 because the diagram in UG-570 is obscure. Below is screen capture of Figure 75 of document UG-570. I have couple questions on that and please kindly help me on them.
1) In figure #75, there has no T2_I and T2_Q. Which place should I to allocate T2_I and T2_Q? In TX_FRAME logical high period or logical low period?
2) AD9361 will use the relationship between TX_FRAME and P0_D[11:0] to assign IQ to TX1 or TX2, am I right?
3) In UG-570, FB_CLK should be a copy of DATA_CLK. Does there has any similar requirement for RX_FRAME and TX_FRAME?
Thanks in advance.