Referred to datasheet of AD9361 Pin H12 is a power input and should be powered by a voltage of 1.2V to 2.5V.
In our application we use AD9361 in CMOS-Mode. VDD_Interface (pin H12) is powered from a SMPS based on ADP2164 via CLC-Filter (1.8V - design is an overtake from AD9361-Eval-Board AD-FMCOMMS3-EBZ). Having a brand-new AD9361-chip we measure about 2.22V at this 1.8V-rail. With ferrit in CLC-filter disassembled voltage at AD9361 side (VDD_INTERFACE and pin H12) increase up to 2.48V.
After the first initialization of AD9361 (with ferrit unmounted) voltage at pin H12 decrease down to about 1.8 V. After reassembling of ferrit circuitry works fine.
In order to check if there is another voltage-rail which implies this phenomenon all pullups connected to VDD_INTERFACE were unmounted (e.g. pullup to RESETB etc.) so that VDD_INTERFACE has a connection to pin H12 only. We can definitively exclude that VDD_INTERFACE has any connection to another signal or power-rail than to pin H12 of AD9361. Even in that case we measured about 2.48V when using a brand-new AD9361-chip and about 1.8V after first initialization respectively.
Using a brand-new AD9361-chip pin H12 seems to be an output initially.
We don't really understand how to switch pin H12 from OUTPUT to INPUT by software. Something during initialization must switch between these two operating conditions.
Having an explanation for this phenomenon would be a big advantage.
Thanks in advance for your help.