We are currently using the FMCADC2 reference design and are starting to use it on a new base card of our own design. For routing purposes the differential lines for each JESD204B rx pair have been reversed.
Xilinx indicates that the polarity of the GT transceivers can be changed in HW (eg. Verilog), however I can't figure out which of the following blocks such a change would be made in: util_ad9625_gt, axi_9625_gt or axi_ad9625_jesd
Any help would be appreciated.
Note - I think the polarity can also be changed in SW, but it doesn't look like the ADI driver supports this.