Yes, the LVPECL driver config would be similar to the LVDS example. LVPECL and LVDS will typically have different common modes and differential peak-peak swing levels, but both signaling protocols are accommodated by the ADC by virtue of the AC coupling caps required at the CLK+/- Inputs.
The max sampling rate of the AD9684 parallel LVDS output model is indeed 500MSPS. Table 16 in the AD9684 rev0 datasheet inadvertently reflects the DDC Filter capabilities of the JESD204B output enabled model which does support a sampling rate of 1Gsps. Thanks for bringing this to our attention. We will correct the table in our next revision of the AD9684 datasheet. The corrected AD9684 Table 16 is shown below.
thanks for comment's.
here is table 3 in the AD9684 datasheet.The AD9684 clock inputs support LVPECL, but there is no mention of the recommended circuit for the LVPECL standard in Figure 50-51.Does the chip support this standard?
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