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BF707 SPI Master DMA Mode Receive Trouble

Question asked by bahattinkocaman on Nov 15, 2016
Latest reply on Nov 21, 2016 by Prashant

hi,

my setup is eval-bf707-ez-kit lite evaluation board and a custom design sensor board. custom board was designed to match p1a, p1b, p1c connectors of ez-kit. there is a adc (ads8568) on the custom board. adc outputs data over the serial (spi) interface. it is designed to be used in software mode which means, it is need to be configured over spi.

 

the adc takes samples every 22.6us (44.1KHz). each sample is 16bytes. maximum clock frequemcy of adc spi is 45Mhz.

there is huge amount of data to deal with. so the best practice will be spi dma.

 

to configure the adc, i need to transmit 4bytes configuration data to the adc over spi. once the configuration is done. there is no need to transmit. after configuring the adc, i need to receive 16bytes data from adc over spi, repeatedly (44100 samples per second each 16bytes).

 

i configured dma tx channel of spi0(i get some help from 2 project files share in this forum, so most of functions will be familiar to contributers.) when dma4 and spi is enabled, i can track spi clock by osiloscope.

if i am wrong please correct me. to initiate the transfer txctl_tti should be set.

*pREG_SPI0_TXCTL |= ENUM_SPI_TXCTL_TX_EN | ENUM_SPI_TXCTL_TTI_EN;

 

my #1 master problem is

if i do not configure spi0 dma5 rx, spi0 dma4 tx generates clock as expected. spi0 dma tx configures the adc. the adc starts to generate interrupt outputs. when i set rxctl_rti, adc crashes/stops responding. what i mean from crashing is one of adc's operating mode is generating interrupt outputs to warn uc/dsp, the conversion is done, the digitized data is ready, you can initiate spi rx.

if i do not set rxctl_rti, spi0 dma5 rx does not start, spi0 does not generate any clocks. nothing happens on miso and cs and clock line.

 

my #1 minor problem is

if i want to repeat any tx or rx transmission in stop mode(assume that autobuffer is not an options). for example i need to receive 16bytes at 44100Hz and transmit 4bytes at 100Hz repeatedly. there should be a suggested reload procedure. which specific registers should be reconfigured?? do i need to disable spi peripherial spi_ctl &= ~en ??? or do i need to disable spi first than dma afterwards and reset spi_ctl register and enable dma first and spi afterwards??? what is the reload routine??. i found nothing about stop mode reloading in hardware referance manuel.

 

i attach my zipped project file and osiloscope screenshots.

i hope you help me to overcome this trouble.

 

scope_5.bmp: blue is a gpio which's rising edge alerts adc to start conversion periodically, 44100Hz.

yellow is the interrupt output of adc. falling edge of interrupt output means conversion is done, you can grab the data.

nevermind green.

 

scope_2.bmp: yellow is tti and rti is set. three times spi0 dma4 tx, each 4 bytes, one time spi0 dma5 rx, once 16 bytes.

nevermind green and blue.

 

scope_7.bmp:  yellow is a gpio which's rising edge alerts adc to start conversion periodically, 44100Hz.

blue should be the interrupt output of adc. but, as i mentioned previously, setting rxctl_rti craches the adc.

 

scope_0.bmp: yellow is tti set, rti is reset. three times spi0 dma4 tx, each 4 bytes, none spi0 dma5 rx. but, go back to scope_5.bmp adc functions as expected. i keeps generating interrupt outputs, just after timer driven gpios rising edge.

nevermind green and blue.

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