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HMC7044 - locking both PLLs?

Question asked by JanBilek on Nov 15, 2016
Latest reply on Nov 22, 2016 by JanBilek

Hi,

 

I'm currently evaluating your HMC7044 using EV3HMC7044LP10B and configuration GUI ver 0.5.3. As indicated in UG-826 I'm injecting 122,88MHz +6dBm sine wave to CLKIN0 from my benchtop RF signal generator. I would like to see some 100 -> 200 MHz clock coming out of the output buffers with minimum jitter possible. I'm also observing "Alarm readback status" bits on the "STATUS" tab to see if both PLLs are locked and running correctly. However, I'm not able to force the chip to run with both PLLs simultaneously locked. (I'm looking at "PLL1 lock detect", "PLL2 lock detect" and "PLL1 and PLL2 lock detect" flags.) I spent hours of trying diverse combinations but no success.I'm able to lock only one PLL at a time but not both of them simultaneously.

 

Could you please post here or send me an email with *.py configuration file which would show both PLLs locked simultaneously? ...I assume that when I try to minimize jitter I need to have both PLLs locked, right?

 

Also, I would appreciate some help file that would explain me some of the configuration items in the GUI since not everything can be traced to the datasheet.

 

Thank you in advance for your support.

Best regards,

Jan.

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