I'm using adv7393 in Slave timing mode 2 for SD CVBS output. I have seen its manual so many times but still unable to identify these issues.
- Since for the above mentioned mode the timing reference signal Hsync and Vsync are used, and Hsync and Vsync should be asserted low before 264 clock cycles before active pixel data. But for how long the Hsync and Vsync should be asserted low, this information I did not find.
- I have tried providing Hsync and Vsync for one clock cycle and 2 clock cycles, but still not getting the image displayed properly. The image is rolling horizontally and flickering also. Here is the link for TestVideo . .
|Header 1||Header 2|
|Input Format||10 bit 625i YCrCb|
|Synchronization format||HSYNC (31.5KHz)/ VSYNC(60Hz)|
|Input Color Space||YCbCr|
|Output Color Space||CVBS/Y-C Out|
Please tell me if i am missing something.