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Can AD9694 support the simple 500[Msps] 14-bit Quad ADC operations with disabling any filtering function built-in AD9694?

Question asked by SKBY on Nov 15, 2016
Latest reply on Jan 23, 2017 by SKBY

Dear all experts,

My customer asked me about the following questions. Please advise me about your feedback on the following questions.

 

Q1:

Can my customer bypass all bandwidth limitation filters implemented in the DDC block of AD9694?

Or

Can my customer bypass all of the DDC functions of AD9694?

 

Q2:

Can my customer use AD9694 as the simple A/D converter at 125[Msps] with disabling any decimation/band-pass/low-pass/gain filter built-in AD9694?

 

Let me show you the following of my investigation result:

[My investigation result]:

A) Major result: The DDC operations of AD9694 except HB1 can be disabled or bypassed. The HB1 of AD9694 is always enabled and cannot be bypassed. However, the decimation ratio of the HB1 can be set to "1". The decimation rate at 1 will mostly equal to bypassing the HB1.

 

However, in the above application, "Complex to real conversion" must be disabled for the transparent mode required by the customer. However, when "Complex to real conversion" is disabled, the decimation rate of the HB1 will be "2" and not be able to be set to "1".

 

So, AD9694 can support the simple A/D conversion function without any filtering for upto 125[MHz] signal with 500[Msps] because the decimation rate of the HB1 is "2".

 

Is the above of my idea correct?

 

 

Let me show you the following investigation results except the above one:

[My investigation details]:

B) Detailed results:

There are the following descriptions on p.32 of AD9694 datasheet (Rev.0).

 

The DDC (Digital DownConverter) of AD9694 has the following of four blocks:

1) Frequency translation stage:

   ---> "0 Hz IF (ZIF) Mode" must be selected by setting Bits[5:4] of Registers 0x0310&0x0330 to "01"(b) for disabling "Frequency translation stage".

 

2) FIR filter stage:

   HB1 FIR is always bypassed and cannot be bypassed. The decimation rate of the HB1 will set to "2" because "Complex to real conversion" is disabled.

   The HB2, HB3, and HB4 FIR filters are optional and can be bypassed for higher output sample rates.

   ---> The decimation rate of the HB1 will be set to "2" and HB2 through HB4 must be bypassed for disabling the HB1 through the HB4 for upto 125[MHz] signal with 500[Msps] by setting Bits[1:0] of Registers 0x0310&0x0330 to "11"(b).

 

3) DDC gain stage:

   Each DDC contains an independently controlled gain stage. The gain is selectable as either 0 dB or 6 dB.

   ---> The DDC gain must be set to 0[dB] by setting Bit[6] of Registers 0x0310&0x0330 to "0" for disabling the DDC gain stage.

 

4) DDC complex to real conversion as illustrated on p.44 of AD9694 datasheet::

   Each DDC contains an independently controlled complex to real conversion block.

   ---> The following of two register setting must be done for bypassing "Complex to real conversion" block:

         1) "Real mixer" must be selected by setting Bit[7] of Registers 0x0310&0x0330 to "0"(b).

         2) "Complex to real conversion" must be disabled by setting Bit[3] of Registers 0x0310&0x0330 to "0"(b),

 

 

Thanks and regards.

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