I'm in the process or porting the reference design for the AD-FMCOMMS3-EBZ board from the Kintex 7-Series KC705 platform to the Kintex UltraScale KCU105 platform. I'm currently planning on running the software from internal BRAM blocks and I'm only interested in obtaining samples from one of the ADC's on channel RX-1A.
During the porting process I have removed several components including the DDR3 controller, DMA controllers for both the DAC and ADC, ad9361_dac_upack, ad9361_tdd_sync, AXI Interconnect, Linear Flash, etc and all the associated ports (e.g. tx_clk_out, tx_frame_out, tx_data_out, tdd_sync_t, etc.). Since I removed the DDR3 controller, I also had to regenerate the 100 MHz (sys_cpu_clk) and 200 MHZ (sys_200m_clk) clocks using the clocking wizard IP generator and connected them to all the same signal points that were connected with the DDR3 block was used.
I have successfully generated a .bit file from Vivado and used the SDK to compile the No-OS software for this project with the console mode turned on. The software successfully runs out of the MicroBlaze and the command menu appears. Unfortunately, the ad9361_digital_tune() function for the Rx only fails but I'm able to issue several commands that properly query the internal registers and allow me to change various parameters (e.g. Rx sample rate, Rx bandwidth, etc.).
Upon further inspection, I see that the Integrated Logic Analyzer (ILA) that captures samples coming out of the ad9361_adc_fifo appear to be all zeros. I have also turned on the BIST function to generate a tone internally but I still see nothing but zeros captured by the ILA.
I believe I have everything connected correctly but is there perhaps something simple I'm missing that would prevent the axi_9361 block from generating samples? Is there one, or more, critical signals that I inadvertently removed / disconnected that needs to be re-connected to this block in order to have the ADC's generate samples?
Any feedback would be appreciated.