Your drawing of the AD1937 in Single-Line Daisy-Chain TDM mode for both ADC and DAC paths is correct. I would make one small addition: the AD1937(First) has ASDATA2 and DSDATA2 pins. The ASDATA2 pin of AD1937(First) should be connected to GND on order to keep the ADC TDM stream clean as it is originated in that part and sent to AD1937(Second).
How many channels will be in your TDM stream? What sample rate(s) will you be using? Which part will be the clock master? I will be happy to help you with your register settings for this system.
Thank you very much for your answer.
I have a plan to use 16channels with 48kHz, Is it possible? And both DSP and AD1937 have own clock master.
AD1937 clock will get from external audio clock generator not from DSP.
I thought that MCLK will be 48*512fs and direct MCLK mode, set sample rate to 48kHz, serial format to TDM single-line modes,and BCLK to 512.
Is there something wrong, please give me your guide.
That sounds fine. If I understand correctly, MCLK = 24.576 MHz will be generated by an external source. Are you going to run both ADC and DAC ports in 16-channel mode? Which part will be generating BCLK and LRCLK? It is not necessary for MCLK to be phase locked with the serial clocks BCLK and LRCLK, but MCLK must never cross edges with them. BCLK and LRCLK must be properly timed against each other, however. I would recommend that you use one of the AD1937 ADC ports as a BCLK and LRCLK Master for the whole system.
There is an eval board for this part: EVAL-AD1937AZ if you would like to test the modes before building your board.
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