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How do I get the outputs of two separate AD9959 chips to have the same phase every time when I initialize them?

Question asked by jpotter0 on Nov 14, 2016
Latest reply on Dec 9, 2016 by JLKeip

I am trying to synchronize two AD9959 chips. I am working with the AD9959 Eval board at this time. I thought I could synchronize the chips by the following process: 1. turn off the common REF_CLK using an AD9508 distribution EVAL board., 2.Reset both chips., 3. Load the input registers with the frequency (same frequency exactly for both units), amplitude and phase offset. 4. Assert IO_UPDATE. 5. Turn on the REF_CLK. 6. Turn off IO_UPDATE. The CSB is held low during this time.

 

The idea is that the the phase accumulator registers and the sync dividers would be set to the same state by the RESET pulse. Then turning on the clock would guarantee that the phase accumulator and the sync clock would star together.

 

However, what I observe is that there is about a 6 us delay between when the REF_CLK is turned on and when the SYNC_CLK appears. I have no way of knowing whether the delays on the two chips match, except that I can compare the phase of the two outputs and I see that they are never the same phase. Each time I try to synchronize I get a different phase.

 

Before you ask why I am not just using the multiple outputs of one chip, I need to tell you that ultimately I need to synchronize more than 10 devices. I am actually deriving my signal from two outputs of the DDS chip in a way that preserves the phase of the output.

 

I  then looked at the AD synchronization scheme. That looks simple enough. I connected the SYNC_OUT of my MASTER unit to the SYNC_IN of the SLAVE UNIT and programmed FR2 accordingly. I observed an approximately 4 ns difference between the rising edges of the two SYNC_CLK signal, I programmed a delay of 3 into the SLAVE FR2. This resulted in a 0.5 ns delay in the SLAVE SYNC_CLK relative to the MASTER SYNC_CLK.

 

I don't see how synchronizing the timing of the SYNC_CLK pulses has anything to do with synchronizing two units, other than insuring that CH0 in one unit matches CH0 in the other unit. What I want is that the phase accumulators in the two chips are set to 0 simultaneously. The only way I see to do that is by setting the frequency input registers and then issuing an IO_UPDATE simultaneously to both units. I actual am doing that, but my IO_UPDATE pulse has a 3 ns risetime which is apparently not fast enough to do the job.

 

Ultimately we are going to synchronize the units by controlling them with an FPGA that is fast enough to issue an IO_UPDATE in all units at exactly the same time. But, right now I am attempting to get a microcontroller to synchronize the units. It sounds like I may not be able to do this.

 

Any advice would be greatly appreciated.

 

Thanks, Jim

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