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AXI DMA wrong behavior (repeats some data values)

Question asked by sauka on Nov 11, 2016
Latest reply on Nov 11, 2016 by larsc

Hi everyone,

 

I've customized AD-FMComms2-EBZ  HDL Reference design, version R2014.2, and added one custom block, which receives data samples from PS through AXI DMA engine, then sends some data to AD9361. Connections are as follows:

 

ProcSystem[HP3 port] --> AXI-DMA[read channel M_AXI_MM2S] --> [write to my block using M_AXIS_MM2S port] --> Custom-IP[S_AXIS].

 

I have Chipscope ILA cores connected to both M_AXI_MM2S port (so, I can check data stream from Processor to DMA) and M_AXIS_MM2S port, allowing to see what DMA sends to my IP.

The problem is that DMA reads valid data from PS side, but writes wrong data to custom IP. In particular it repeats some samples.

 

Here is a stream from PS to DMA (value 1 is at clock cycles 2 and 3, exactly what I'm sending). 

 

And here is a stream from DMA to custom IP (value 1 repeats many times):

Some details:

- DMA IP and my custom block work at 200Mhz.

- DMA IP configuration: SG mode and microDMA are disabled, I use only Read channel, Data width is 32 bits, Burst size is 32 bits, Width of buffer length register is 32 bits.

- Custom IP always holds TREADY signal high.

- I run my program under Linux (ADI kernel).

- I have checked 'Allow unaligned transfers' for AXI DMA and added to devicetree these lines 

xlnx,include-mm2s-dre = <0x1>;  

xlnx,include-dre = <0x1>;

- I wrote custom proxy driver, which acquires DMA channel, and performs transfer to my IP. I tested my Linux kernel driver and test app with simple HDL design having DMA connected to AXIS FIFO as loopback, I used Xilinx kernel 2014.2 and Linaro rootfs. In this system DMA transfer works as expected, all data are correct.

 

 

Could you advise me where can be a problem? Should I also take into account any other configuration/settings? Or some special requirements before modifying reference design?

 

Thanks,

Pavel

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