We have 6 ADCs on a board working in parallel.
After writing c1, c2, gain, overrange, we do a readback to check if it was correctly programmed. Randomly some ADCs of the 6 (1..2..3 ) cannot be configured properly. We found that the source was a strange SCO.
MCLK is 40Mhz (ch2 ), ICLK=MCLK/2, SCO is therefore 20Mhz (ch1).
MCLK is not 5VPP, but we needed a workaround, as we did not have a 5V digital VDD.
But we have the same board where only 2 ADCs are assembled, and there the same setup works and is very stable.
Moreover the issue only occurs after a certain time (~1 min), as the board heats up, and then it get more unstable.
Do you have any hint?