We are using fmcomms2 boards to set up LVDS Full Duplex TDD.
We don't understand how the maximum data rate matches with the reference manual UG763 and other sources.
It says in the following two links (and there is also a limit in software) that the sample rate is limited to 61.44MHz:
But the AD9364 Manual UG673 (it's attached) says that the maximum data rate (combined I/Q) is 122.88MHz.
How can the combined I/Q data rate of 122.88MHz (8ns) be achieved when the Rsamp CLK (RX data) is actually 61.44MHz (16ns) according to AD936x maximum Rx digital path data rates ?
We kind of expected to be able to set the sample rate to 245.76MHz (4 ns) to read interleaved I/Q at DDR, i.e. reading MSB & LSB I/Q at falling and rising edge to have the full I and Q words ready after 8ns.