We have designed custom board with 6 AD9364s with Virtex-7 FPGA.
We have modified the HDL design for 6 AD9364s in Vivado and have made necessary changes in No-OS SDK code with referencing the fmcomms5 design for zynq.
When i run the code the first AD9361 is successfully initialized with no errors, but the other 5 AD9364s give TX tuning Failed! error but they still get initialized.There is no RX tuning error.
I do not observe the LO frequency of the remaining 5 on spectrum analyzer but the first one works.
The first ad9364 has a TX LO at -2dBm at 0 attenuation and the others have TX LO at -60dBm at 0 attenuation which is probably carrier leakage.
Also i have tested all ad9364s individually with individual HDL projects at a time and they all work when tested alone.
I also tried skipping digital tune and calculated the rx_data_clock_delay and tx_data_clock_delay for each IC from the individual projects and still no LO frequency.
What could be the problem here. Any hints? i have attached screenshot of error.
I am ready to share HDL core changes we have made for 6 AD934's.