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Question asked by hpkamen on Nov 8, 2016
Latest reply on Nov 13, 2016 by CsomI

Dear Sir/Madam,


We buied a EVB of KCU105 and FMCDAQ2, and download teh reference design HDL_2016_r1 from below link,

Releases · analogdevicesinc/hdl · GitHub

According the user guide, using vivada with version of 2015.4.2, we configure the  board, however there are some error during generating bit document.

1.message windows erros info:

[Common 17-69] Command failed: This design contains one or more cells for which bitstream generation is not permitted:

i_system_wrapper/system_i/axi_ad9144_jesd/inst/i_system_axi_ad9144_jesd_0 (jesd204_v6_2_1_top)

i_system_wrapper/system_i/axi_ad9680_jesd/inst/i_system_axi_ad9680_jesd_0 (jesd204_v6_2_1_top__parameterized0)


2.Log window info:

error copying "daq2_kcu105.runs/impl_1/system_top.sysdef": no such file or directory

    while executing

"file copy -force $project_name.runs/impl_1/system_top.sysdef $project_name.sdk/system_top.hdf"

    invoked from within

"if [expr [get_property SLACK [get_timing_paths]] < 0] {

    file copy -force $project_name.runs/impl_1/system_top.sysdef $project_name.sdk/system_top_..."

    (procedure "adi_project_run" line 26)

    invoked from within

"adi_project_run daq2_kcu105"

    (file "./system_project.tcl" line 19)

Does this mean  JESD204 has any problem or others.