In Table 7 on page 9 of the AD9154 datasheet it says that the LATENCY VARIATION SPECIFICATION in subclass 1 with PLL off is 1 DACCLK cycle MAX.
What does that mean? Or in more detail:
Is this a variation from unit to unit?
Is this a variation from one SYNC/CGS/ILAS to another SYNC/CGS/ILAS sequence?
Is this a variation over time/voltage/temperature?
Is this a digital variation/non-determinism (i.e. 0 or +1 cycle and no fractional part)?
Does this contradict the "fixed latency" claim on the front page of the datasheet?