I have a question about "HDCP enable timing" of HDMI transmitter ADV7511W.
When HDMI cable is connected, the flow of the HDMI source system is executed as follows:
1. The HDMI source detects HPD = High.
2. The HDMI source reads the EDID of the HDMI sink.
3. The CPU or something on the source writes the information (the resolution etc.) to the related registers of ADV7511W.
4. HDCP is enabled. (Frame Encryption Bit & HDCP Enable Bit(0xAF : bit4, bit7) = 1)
Is there any condition or restriction of the timing of "4. HDCP is enabled" ?
Just after the "3", the TMDS outputs of ADV7511W is unstable.
It can cause problems when HDCP is enabled just after the "3".