We are using AD9361 Rx AGC in manual gain control mode with full table gain index writes from the SPI to register 0x109.
We are measuring the time for the new gain to take effect on the rx chain. This is done by triggering the logic analyzer to capture the received digital IQ data on SPI gain write to register 0x109 in the FPGA. These lines are probed out to the debug board for this purpose.
We see that the gain takes effect on the received digital IQ after ~70 microseconds (actually it varies between ~70 microseconds to ~100+ microseconds, depending on if we are programming from the SPI script using the direct_reg_access or through the GUI).
First, is this gain update time correct?, Next, Would like to know if there is any specific register setting of AD9361 which will reduce this time for the gain to take effect on the receiver chain.
Look forward to your advice.