I'm trying to get Phase Resync implemented in our design and I've run into an issue where as soon as the feedback select is set to "Divided" I no longer see lock detected asserted. I've tried both digital and analog lock detect to the same result.
Phase resync aside, everything else seems to be functioning just fine when the feedback select is set to "fundamental", as in I'm able to tune around, see a lock detected, and see the correct frequency,
I've included the values of the registers that we're programming when attempting to run with a "Divided" feedback select setting.
These values are for a target frequency of 3.345 GHz given a PFD freq of 6.25MHz from a reference frequency of 50 MHz.
Searching around I've been unable to find a reason for this failure to lock.
I also have some additional questions:
- In the ADF5355 FAQ posted on this board the answer to "Question: Is the ADF5355 phase coherent?" has this line
"ADF5355 can achieve this using the Phase Resync, REG 3 [DB29] feature as long as FRAC2 = 0 and as long as Phase Adjust, REG 3 [DB28] is not being used at the same time. "
I haven't been able to find the FRAC2=0 requirement anywhere else, is this actually a requirement to get phase resync functioning?
- The Fractional-N Lock Detect Precision (LDP) bit explanation in the data sheet states to use 12 ns if bleed currents are used. Which bleed currents is it referring to? Charge pump? Gated? Negative? Any/all?
Thanks for you help,