I would like to use the adxl355 because of its low noise performance. However, I am running into challenges when it comes to integrating it with my existing platform. Typically, I base my sampling timing off a 32.768kHz crystal. However, if I fed this clock directly into the adxl355, we would get a maximum sample rate of 512Hz. This is too low. We would like a max of 4096Hz. Our options appear to be the following:
From the data sheet, here are my options as I understand them:
1) use the adxl355's internal clock
2) use the internal clock and the interpolation filter and upsample.
3) using an external xtal as the master clock and sync externally
In general, I guess I am wondering, given the limitations of my system, what is the best method for getting quality, synchronized data from the adxl355. Here are some specific questions.
1) What is the max ODR (not using the interpolation filter)? Is it 4kHz or can you go higher? Specifically, would the adxl355 support an ODR of 4096? If it can, how could I calculate the group delay?
2) A forum post stated that the internal clock produces a sample rate error of ~3.5% ADXL355 Sampling Frequency
Is this over temperature or just at room temp? What about jitter?
3) A follow up to question 2: is the internal clock an RC oscillator or a xtal?
4) What is the accuracy of data produced by the interpolation filter?
5) What is the impact on power consumption of using the interpolation filter?
6) The interpolation filter adds attenuation to the signal. How can I calculate the expected -3dB point?
7) When using the interpolation filter, is the delay going from standy to active mode still <10mS?
8) The data sheet mentions some distortion and spectral degradation when using the interpolation filter. Could you provide more details?
9) The current consumption (200uA) mentioned in the datasheet assumes a 500Hz ODR. Do you have any data on how the current consumption changes with ODR?
10) On page 29, the datasheet mention that when you are using external clock and syncing externally, that "the phase of sync must meet an approximate 25nS setup time to the EXT_CLK rising edge." I take this to mean that rising edge of the sync line must occur withing 25nS of the rising edge of the clock. Am I right? And secondly, what happens if this is not the case? This is a very tight tolerance for us to meet.
Thanks in advance for your reply.