What is the max/min/typical latency between the DataIn and DataOut Signal? Is it depending on any settings?
ADN2816 is one any rate CDR, supports any rate input signal in the range of 10Mbps to 675Mbps.
It provides superior jitter performance to continuous mode data streams used in SONET and SDH systems .
With a proprietary dual loop control, this CDR uses a complex process to determine the latency, depends on input signal data rate, signal integrity, signal noise/jitters, and CDR operation environment.
ADN2816 is designed to support SDH and SONET data link applications. In these applications, latency is not a required technical specification. Therefore, we didn't specify the latency in ADN2816 datasheet.
Could you please elaborate your target applications, data rate, and system min. latency required in your target application? In a specified application scenario, we might have some better answer for you.
The data rate of the Data Input Signal would be typically in the range of 100-200Mbps.
The recovered clock Signal is used to sample the data Output Signal. However, there are further data signals which are sychronous to the original clock (clock as coded in the Data Input Signal). To sample this further signals with the recovered clock, the delay between Input and Output should be << clock rate.
Does this make sense?
ADN2816 extracts an embedded clock from a serial input data stream. ADN2816 then uses the recovered clock to sample the ADN2816 input data stream to get the recovered data. During the process, ADN2816 will align recovered clock edges to an optimal position of input signal eye, to get best BER performance, automatically.
Therefore, the latency from data input to recovered data output will be signal rate, signal quality, and applications environment dependent.
Since ADN2816 is designed to support serial link, asynchronized communication system applications, variety CDR device latencies, if any, doesn't matter to the target applications. So the datasheet has no such specification.
However, if you do system synchronization design, try to use the CDR recovered clock as a local timing source to sample other system device output signals, you would see timing skew.
I would recommend to get one ADN2816 evaluation board, find out the ADN2816 latency with your target applications rate, signal source, and application environments. Please note, you might find latency mean and sigma range at the applied application scenario.
Hope these are useful to you.
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