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Help with VGA configuration on ADV7842

Question asked by dgomeziseebcn on Nov 3, 2016
Latest reply on Nov 8, 2016 by GuenterL

Hi,

 

I'm trying to test VGA over the ADV7842 using evaluation board: EVAL-ADV7842-7511

 

For doing this I have using this input resolution: 1280x1024@60 and script configuration located in ADV7842-VER.5.9c.txt (script :5-1e). Once script is executed I'm changing PRIM_MODE and VID_STD according to the input resolution:

- PRIM_MODE = 0x02 (GR mode)

- VID_STD = 0x07 (autographics)

But I can not see anything on the HDMI output which is connected to a monitor.

 

Note: I have also teste with VID_STD value 0x05 but the result is the same.

 

Maybe I have to configure more parameters and changing others. Could anyone help me?

 

 

Thanks

 

This is the script 5.1e:

:5-1e 640x480@60 VGA RGB in_ 444 24bit H_V_DE DVI:
50 10 05 ; Data output mode
50 11 08 ; Bus Reversal
50 19 10 ; ADV7842 Mode
50 1B 02 ; ADV7511
40 FF 80 ; I2C reset
40 F1 90 ; SDP map
40 F2 94 ; SDPIO map
40 F3 84 ; AVLINK
40 F4 80 ; CEC
40 F5 7C ; INFOFRAME
40 F8 4C ; AFE
40 F9 64 ; KSV
40 FA 6C ; EDID
40 FB 68 ; HDMI
40 FD 44 ; CP
40 FE 48 ; VDP
40 00 08 ; VID_STD=01000b for VGA60
40 01 82 ; Prim_Mode to graphics input
40 02 F6 ; Auto input color space, Limited Range RGB Output
40 03 40 ; 24 bit SDR 444
40 05 28 ; Disable AV Codes
40 0C 40 ; Power up Part
40 15 B0 ; Disable Tristate of Pins except for Audio pins
44 73 EA ; Set manual gain of 0x2A8
44 74 8A ; Set manual gain of 0x2A8
44 75 A2 ; Set manual gain of 0x2A8
44 76 A8 ; Set manual gain of 0x2A8
44 85 0B ; Disable Autodetectmode for Sync_Source for CH1. Force CH1 to use HS&VS
44 C3 39 ; ADI recommended write
4C 0C 1F ; ADI recommended write
4C 12 63 ; ADI recommended write
4C 00 80 ; ADC power Up
4C 02 00 ; Ain_Sel to 000. (Ain 1,2,3)
4C C8 33 ; DLL_PHASE - 110011b
72 01 00 ; Set 'N' value at 6144
72 02 18 ; Set 'N' value at 6144
72 03 00 ; Set 'N' value at 6144
72 15 00 ; 24-bit, 444 RGB input
72 16 00 ; RGB 444
72 18 46 ; Disable CSC
72 40 80 ; General control packet enable
72 41 10 ; Power down control
72 49 A8 ; Set dither mode - 12-to-10 bit
72 96 20 ; HPD interrupt clear
72 56 08 ; Set active format aspect
72 98 03 ; ADI recommended write
72 99 02 ; ADI recommended write - lock count limit
72 9C 30 ; PLL filter R1 value
72 9D 61 ; Set clock divide
72 A2 A4 ; ADI recommended write
72 A3 A4 ; ADI Recommended Write
72 A5 44 ; ADI Recommended Write
72 AB 40 ; ADI Recommended Write
72 AF 14 ; Select DVI mode
72 BA A0 ; Set TX Clock Delay
72 DE 9C ; ADI recommended write
72 E4 60 ; VCO_Swing_Reference_Voltage
72 FA 7D ; Nbr of times to look for good phase
End

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