We know that AD9371 has JESD204B interface supports four lanes for Tx data and four lanes for Rx data,
My question is: how many GTX/GTH transceivers in the FPGA do we need?
Thanks a lot
It depends on your requirement and configuration.
You can configure AD9371 to transmit and receive all samples on one lane each respectively, number of lanes depends on data rate
For more details on JESD configuration refer UG-992 JESD204B interface section
Max lane rate supported is 6144 Mbps
IQ Sample rate = 61.44
M(no of converters) = 4
L(no. of lanes) = 1
Lane rate will be 3145.728 Mbps
you can see we are configuring AD9371 for 1 lane you require 1 GTX/GTH Transceiver in FPGA.
On same lines you can decide selection of no. of GTX/GTH Transceiver in FPGA depending on your requirement.
Thank you for your prompt reply. Another question is: If I configure AD9371 for 1 Tx lane and 1Rx lane ,one GTX/GTH transceiver is needed or two?(i.e. one GTX contain 1 Tx/RX lane pair?)
Can I configure Tx for 1 lane and Rx for two lane? And how many GTX/GTH transceivers should I need ?
You can configure Tx 1 lane and Rx 2 lanes. Number of lanes needs to be same in FPGA as you configure for AD9371.
Tx and Rx/Orx lanes are independent and can be configured between 1 and 4 lanes as per requirement.
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