We have the FMCOMMS5 and Xilinx evaluation board up and running. We have designed our own custom daughter card using the AD9361 but cannot get the BBPLL to lock. We are using the same reference clock input to both boards, 40MHz. I have checked the 1.3V supply and the clocks distributed on the boards and they all appear to be in spec of <1.3Vp-to-p. I put some wait statements into your No-Os code to see if I could see what was going on and I can see that register 0x05E bit 7 does go high but not until moving from Alert to FDD mode. Any advice is appreciated.