I have some question.
About tLIS, the description mentions as below.
"LRCLK setup to BCLK_INx input rising edge"
Could you tell me the exact definition of the rising edge please?
Does this mean exact middle point(1.65V level if the logic range is from 0V to 3.3V) of the rising edge as shown in the figure 5 on Datasheet p.10?
I also have the same question on tSIS as above. rising edge is defined as the middle?
Could you please provide me an answer?
About tSODS, the description says as below
"SDATA_OUTx delay in slave mode from BCLK_OUTx output ”falling edge”."
However, it seems that you measure it with the rising edge on figure 6.
Could you please explain?
About tSODS, when BCLK is 24.576MHz, the BCLK period is 40.7ns. And the half period is 20.35ns.
However, the max of tSODS is defined at 35ns. How is it possible???