a) I am planning to use AD7761 in my design; I want to know what is the Maximum conversion rate (Number of converted data at output lines per second) that i can achieve with this ADC, considering all 8 input channels?
b) From datasheet I understood that it is capable of converting and sending data at 256 Kilo Samples per Second, in parallel, for all 8 Input channels (Considering each DOUT is assigned to one Input Channel).
Does this mean that analog inputs at all "8 channels of ADC will be converted and converted data will be sent out in their respective DOUTx pin", at 256000 times per second (ADC sampling+Conversion+Data transmission)?
Say, i have interfaced this ADC to an FPGA, then at FPGA I will be getting converted data at 2048 (256*8) KSPS. Is this correct?
c) If all my above mentioned understanding are correct, then what is the significance of Settling time (68/ODR) of Digital Filters? What does it mean to my Data Conversion rate? Will it decrease/increase 256KSPS per CH conversion rate of my ADC? If it decreases, how to overcome/bypass this reduction in conversion rate? Refer 'DIGITAL FILTER RESPONSE' at Table 1 in page 5 of AD7761 datasheet.
d) And what is this Decimation Rate? What is the effect of this over my Data Conversion rate? If it decreases my conversion rate, how to overcome/bypass this decimation control? It has been mentioned as 'The decimation rates allow the user to reduce the measurement bandwidth, reducing the speed but increasing the resolution.' ; Refer 'DECIMATION RATE CONTROL' section at page 42.
Thanks and Regards,
Dhinesh kumar Nachimuthu.
ad7761 #ADC conversion rate