I have found register description inside ADRF6820.pdf only. Where I can find initialization sequence or programming examples?
Unfortunately there are no programming examples, but register settings and sequence are explained in the Theory of Operations section. One way to get the correct settings is to use the customer evaluation board GUI and readback the register settings. However it does not give you the correct register write sequence for which you have to look at the Theory of Operation section.
Please let me know if this helps.
Thank you for a quick answer.
I expected to set Enables (reg 01) as a final configuration step but adrf6820.pdf says
Required PLL/VCO Settings and Register Write Sequence
Configure the PLL registers accordingly to achieve the desired frequency, and the last writes must be to Register 0x02 (INT_DIV), Register 0x03 (FRAC_DIV), or Register 0x04 (MOD_DIV). When Register 0x02, Register 0x03, and Register 0x04 are programmed, an internal VCO calibration initiates, which is the last step to locking the PLL.
Can I configure all CTLs and set Enables 0->1 at the end? Will it work correctly?
Is it possible to read lock from registers not from MUXOUT pin?
The lock detect signal is available as one of the selectable outputs through the MUXOUT pin, with a logic high signifying that the loop is locked. The control for the MUXOUT pin is located in the REF_MUX_SEL bits (Register 0x21, Bits[6:4]), and the default configuration is for PLL lock detect.
Where I can find information about these blocks?
Dither (regs 42, 43)
BANDCAL, SIF (regs 44, 45, 46)
I am not exactly sure what you meant with the your first question, but it is probably a better idea to turn on the blocks and set the CTLs. The way you would probably work too.
Unfortunately there is not a register that you can read the lock detect directly.
You do not have to use BANDCAL bits in normal use case scenario, that is why no information is included.
DITH_MAG: Dither magnitude controls the amplitude of the pseudo-random dither signal added to the fractional input to the SDM. The value of 3 I believe corresponds to the minimum amplitude, which is what we typically use.
DITH_VAL: The dither value is actually the seed value for the PRBS block that generates the dither signal.
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