I went through the AD9484 datasheet, and I was a little bit confused in understanding the input common mode section.
According to the datasheet, the optimum input common mode is set to about 1.7 V by CML pin. Since the ADC has a 1.5 Vpp maximum measurement range, I believe the input pins are therefore supposed to swing between 1.325 and 2.075 V, which is violating the absolute maximum specifications by 75 mV (Absolute maximum: 1.8 V + 0.2 V = 2.0 V). What can I do to achieve the full conversion dynamics without exceeding absolute maximum voltage? Also, in the description of Fig. 28, it is stated that "The output common-mode voltage of the AD8138 is easily set to AVDD/2 + 0.5 V"; I don't understand how this is achieved in the circuit in Fig. 28, since the CML pin is stated to supply 1.7 V, and not VDD/2+0.5 = 1.4 V...
Using a lower common mode voltage (e.g. 1.4 V, as stated in this answer) also helps me in simplifying my input amplifier, so at the end of the day I believe I will go in this direction: could you please indicate me what is the exact input common mode voltage range of this ADC (in particular, what is the minimum input common range I can supply), which is not stated in the datasheet? What is exactly the drawback in reducing the input commmon mode voltage to 1.4 V? Is it only a matter of SFDR, or is there some limitation on the 8-bit dynamic range?
Finally, Fig. 21 of the datasheet mentions a VBOOST voltage, whose purpose isn't described elsewhere. Is it something related to the ADC core, or can I simply ignore it?
Thank you for your answers,