The datasheet of ADV8005 says it has 2 mode for TTL output clock timing as below.
Which register can change output timing?
I found the register 0x1ACC can invert OSD_CLK.
Forwarded to ADV8005 expert.
Bit 0x1A1F controls the polarity of the OSD_CLK. It should default to '0' = invert disabled. Note this bit is not defined in the manuals.
Thank you for your response.
Your pointed register doesn't seem to change the polarity of the OSD_CLK.
Are there any other registers that should be set ?
This was the only comment form the ADV8005 expert.
Sorry for my delay.
I tried to change the register 0x1A1F on your evaluation board, but it doesn't seem to change the polarity of the OSD_CLK.
Would you confirm if the register 0x1A1F could control the polarity of the OSD_CLK again?
0x1ACC does invert the OSD output pad. It is intended was intended for inhouse debug and this is why it doesn't show up in the documentation.
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