I am having issues getting the 1 PPS signal from a GPS to work with the AD9548 Eval board. I have seen a few others having the same issue. After working through all the documented ideas I still do not see the 1 PPS signal.
I have the 1 PPS signal which is a 0 to 5 volts pulse connected to Ref A input. Ref A has the C42 removed and replaced with a 33 ohm resistor. R24 has been removed. I have included scope shots of my 1 PPS signal showing the rising and falling edges and duty cycle. No ringing viable with 250 MHz scope.
I have tried many combinations on the software configurations.
The settings I feel should work are:
External XTAL 20 MHz TCXO
Clock Double Checked
Low Detect Timer = 128
Stabilization Period = 0.1 S
Operation Set to Manual Ref A and Holdover
Profile - Built a few profiles and tried them attached to Ref A. - This may be my problem. I have tried adjusting the loop parameters to give more time to settle and sink. Also tried increasing R to have PLL clock closer to 1 PPS input.
DPLL - Tried putting different values in the frequency and assigning them to an output. Don't think this is required to get Ref A to go valid.
Ref A set to 3.3 V CMOS and a Profile (Tried all kinds of other vales as well and tried using other Ref inputs).
Configured all the Status signals (M0 - M7) and set them up to monitor Stable System Clock (H), Ref A Fault (H), Ref A Valid (L), Frequency Lock (L), Phase Lock (L).
I have tried adding a voltage divider (1K + 2K) to reduce 1 PPS input level. Did not help. I have tried with a short on C42. These combinations were suggested in other ap notes and the documentation.
I found it helpful to monitor the system clock with the status bit provided, System Clock/32. I can see my system clock changing states. Is there a way to monitor the 1 PPS clock input to see the signal is getting into the state machine and changing states?
Any suggestions on what needs to be corrected?
Can you provide a profile to try with a 1 PPS signal that has a 60 ns rise and fall time? I assume you are edge triggering on leading edge. Do I need to include a buffer to provide the CMOS levels with a sharper rise time?
Hopefully this posting will be helpful to others as well.