From the manual it looks like inputs 6 and 7 are the SPDIF input. I don't find a description of how to enable SPDIF output.
Also it looks like the SPDIF input defaults to using the ASRC? As we want to construct a "sample accurate" in to out system we would want to bypass the ASRC and slave the SPDIF Tx to the input clock. Can that be done from inside of SS?
Also I don't see a description of how to read the SPDIF Rx status to see if the Rx is locked to a valid stream, with the idea being we would mute the output in that case. A related question is what happens to the clocking in that case.
Thanks for any pointers/information you can provide.