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Visual Analog ADC Data Capture Error

Question asked by alexlpd on Oct 25, 2016
Latest reply on Nov 9, 2016 by DougI



I'm currently using the the AD9656EBZ Eval Board with the HSC-ADC-EVALEZ Data Capture Board. In short, I'm currently just walking through the Evaluation User Guide Wiki. I've been following ever instruction to a "T", but am finding a few issues as I try to generate of an Average FFT of external signal:


  1. Within ADCBase0 tab in the SPI Controller Software, the "PLL STATUS REG(A)" field is reporting "PLL is NOT locked" and "Link is not ready" (Note: DS501 is not on). Any idea what I may be able to try to troubleshoot (outside of supplying an external clock). Some notes:
    • I'm using the onboard oscillator (Y801, it's a 125MHz part)
    • J304 is installed.
    • I have set the clock frequency to 125MHz within the Visual Analog's ADC Data Capture Settings
    • CLOCKDIVIDE(B) = "div by 1" within the ADCBase0 tab in the SPI Controller software
  2. This error is likely caused by the issue I'm detailing above, but when I complete the setup (per the Evaluation User Guide) and click "Run", I received the following error: "ADC Data Capture: Read cannot be performed because FIFO is not ready for readback." Any insight on what might be causing this issue (if it's unrelated to the above)?


I'm going to take several screenshots of my settings and setup; it's attached in the "AD9656EBZ_Issue_20161025.docx". Please review when you have a moment; any guidance at all will be greatly appreciated.