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ADDI7015 : TCLK

Question asked by Mr.K on Oct 24, 2016
Latest reply on Nov 1, 2016 by TFAnalog

Hello,

 

I have some questions about the ADDI7015.

 

Q1:

The AFE has the LVDS output of four channels.

TCLK of the LVDS output separates for the A/C channel and for the B/D channel.

I want to use only either of TCLKx_AC or TCLKxBD.

CLI of AFE is used with 32MHz.

For instance, only the TCLKx_AC is used to transmit the data of A, B, C, and D channel.

In a word, FPGA receives the data of B and D channel with the TCLKx_AC clock.

Is it possible?

 

Q2:

I not use neither XVx nor the Hx signal.

I will non connect these terminals.

Is it all right?

 

Best Regards,

Mr.K

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