AnsweredAssumed Answered

SDRAM Timing

Question asked by moerte on Oct 24, 2016
Latest reply on Dec 9, 2016 by Jithul_Janardhanan

Hello,
i am using an ADSP-BF523 and an Elite SDRAM M12L64164A-5BIG2Y.
The external busclock is 100MHz and the SDRAM-Timings are:
*pEBIU_SDRRC = 0x612;
*pEBIU_SDBCTL = EBCAW_8 | EBSZ_16 | EBE;
*pEBIU_SDGCTL = PSS | TWR_2 | TRCD_2 | TRP_2 | TRAS_6 | CL_2 | SCTLE;

Sometimes the Memory-Access is corrupted and wrong Data is read from the SDRAM-Device.
If i use the 200ps OUTPUT-DELAY-Option in the PLL control register the access succeeds.

Is the Elite Ram compatible to the BF523?

Are the setup and hold times calculated like this?

for data to sdram:
setup: tSCLK-tDCAD = 10ns - 4ns = 6ns
hold: tHCAD = 1ns

for data from sdram:
setup: tSSDAT = 1.5ns
hold: tHSDAT = 0.8ns

In ee326 page 9 there is tHSDAT mentioned for write to SDRAM.
I think this timing parameter is for reading from sdram.
Can you please explain this.

 

Whitch signals are affected by the OUTPUT-DELAY and INPUT-DELAY Option in the PLL control register.
Is this an option just for SDRAM-controller or for the async-controller too?

 

Thanks
Bernhard

Outcomes